/**
 * \file IfxInt_bf.h
 * \brief
 * \copyright Copyright (c) 2019 Infineon Technologies AG. All rights reserved.
 *
 *
 * Version: TC38XA_UM_V1.1.0.R0
 * Specification: TC3xx User Manual V1.1.0
 * MAY BE CHANGED BY USER [yes/no]: No
 *
 *                                 IMPORTANT NOTICE
 *
 *
 * Use of this file is subject to the terms of use agreed between (i) you or 
 * the company in which ordinary course of business you are acting and (ii) 
 * Infineon Technologies AG or its licensees. If and as long as no such 
 * terms of use are agreed, use of this file is subject to following:


 * Boost Software License - Version 1.0 - August 17th, 2003

 * Permission is hereby granted, free of charge, to any person or 
 * organization obtaining a copy of the software and accompanying 
 * documentation covered by this license (the "Software") to use, reproduce,
 * display, distribute, execute, and transmit the Software, and to prepare
 * derivative works of the Software, and to permit third-parties to whom the 
 * Software is furnished to do so, all subject to the following:

 * The copyright notices in the Software and this entire statement, including
 * the above license grant, this restriction and the following disclaimer, must
 * be included in all copies of the Software, in whole or in part, and all
 * derivative works of the Software, unless such copies or derivative works are
 * solely in the form of machine-executable object code generated by a source
 * language processor.

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
 * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE 
 * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * \defgroup IfxSfr_Int_Registers_BitfieldsMask Bitfields mask and offset
 * \ingroup IfxSfr_Int_Registers
 * 
 */
#ifndef IFXINT_BF_H
#define IFXINT_BF_H 1

/******************************************************************************/

/******************************************************************************/

/** \addtogroup IfxSfr_Int_Registers_BitfieldsMask
 * \{  */
/** \brief Length for Ifx_INT_ID_Bits.MOD_REV */
#define IFX_INT_ID_MOD_REV_LEN (8u)

/** \brief Mask for Ifx_INT_ID_Bits.MOD_REV */
#define IFX_INT_ID_MOD_REV_MSK (0xffu)

/** \brief Offset for Ifx_INT_ID_Bits.MOD_REV */
#define IFX_INT_ID_MOD_REV_OFF (0u)

/** \brief Length for Ifx_INT_ID_Bits.MOD_TYPE */
#define IFX_INT_ID_MOD_TYPE_LEN (8u)

/** \brief Mask for Ifx_INT_ID_Bits.MOD_TYPE */
#define IFX_INT_ID_MOD_TYPE_MSK (0xffu)

/** \brief Offset for Ifx_INT_ID_Bits.MOD_TYPE */
#define IFX_INT_ID_MOD_TYPE_OFF (8u)

/** \brief Length for Ifx_INT_ID_Bits.MOD_NUMBER */
#define IFX_INT_ID_MOD_NUMBER_LEN (16u)

/** \brief Mask for Ifx_INT_ID_Bits.MOD_NUMBER */
#define IFX_INT_ID_MOD_NUMBER_MSK (0xffffu)

/** \brief Offset for Ifx_INT_ID_Bits.MOD_NUMBER */
#define IFX_INT_ID_MOD_NUMBER_OFF (16u)

/** \brief Length for Ifx_INT_SRB_Bits.TRIG0 */
#define IFX_INT_SRB_TRIG0_LEN (1u)

/** \brief Mask for Ifx_INT_SRB_Bits.TRIG0 */
#define IFX_INT_SRB_TRIG0_MSK (0x1u)

/** \brief Offset for Ifx_INT_SRB_Bits.TRIG0 */
#define IFX_INT_SRB_TRIG0_OFF (0u)

/** \brief Length for Ifx_INT_SRB_Bits.TRIG1 */
#define IFX_INT_SRB_TRIG1_LEN (1u)

/** \brief Mask for Ifx_INT_SRB_Bits.TRIG1 */
#define IFX_INT_SRB_TRIG1_MSK (0x1u)

/** \brief Offset for Ifx_INT_SRB_Bits.TRIG1 */
#define IFX_INT_SRB_TRIG1_OFF (1u)

/** \brief Length for Ifx_INT_SRB_Bits.TRIG2 */
#define IFX_INT_SRB_TRIG2_LEN (1u)

/** \brief Mask for Ifx_INT_SRB_Bits.TRIG2 */
#define IFX_INT_SRB_TRIG2_MSK (0x1u)

/** \brief Offset for Ifx_INT_SRB_Bits.TRIG2 */
#define IFX_INT_SRB_TRIG2_OFF (2u)

/** \brief Length for Ifx_INT_SRB_Bits.TRIG3 */
#define IFX_INT_SRB_TRIG3_LEN (1u)

/** \brief Mask for Ifx_INT_SRB_Bits.TRIG3 */
#define IFX_INT_SRB_TRIG3_MSK (0x1u)

/** \brief Offset for Ifx_INT_SRB_Bits.TRIG3 */
#define IFX_INT_SRB_TRIG3_OFF (3u)

/** \brief Length for Ifx_INT_SRB_Bits.TRIG4 */
#define IFX_INT_SRB_TRIG4_LEN (1u)

/** \brief Mask for Ifx_INT_SRB_Bits.TRIG4 */
#define IFX_INT_SRB_TRIG4_MSK (0x1u)

/** \brief Offset for Ifx_INT_SRB_Bits.TRIG4 */
#define IFX_INT_SRB_TRIG4_OFF (4u)

/** \brief Length for Ifx_INT_SRB_Bits.TRIG5 */
#define IFX_INT_SRB_TRIG5_LEN (1u)

/** \brief Mask for Ifx_INT_SRB_Bits.TRIG5 */
#define IFX_INT_SRB_TRIG5_MSK (0x1u)

/** \brief Offset for Ifx_INT_SRB_Bits.TRIG5 */
#define IFX_INT_SRB_TRIG5_OFF (5u)

/** \brief Length for Ifx_INT_SRB_Bits.TRIG6 */
#define IFX_INT_SRB_TRIG6_LEN (1u)

/** \brief Mask for Ifx_INT_SRB_Bits.TRIG6 */
#define IFX_INT_SRB_TRIG6_MSK (0x1u)

/** \brief Offset for Ifx_INT_SRB_Bits.TRIG6 */
#define IFX_INT_SRB_TRIG6_OFF (6u)

/** \brief Length for Ifx_INT_SRB_Bits.TRIG7 */
#define IFX_INT_SRB_TRIG7_LEN (1u)

/** \brief Mask for Ifx_INT_SRB_Bits.TRIG7 */
#define IFX_INT_SRB_TRIG7_MSK (0x1u)

/** \brief Offset for Ifx_INT_SRB_Bits.TRIG7 */
#define IFX_INT_SRB_TRIG7_OFF (7u)

/** \brief Length for Ifx_INT_OOBS_Bits.OTGB0 */
#define IFX_INT_OOBS_OTGB0_LEN (16u)

/** \brief Mask for Ifx_INT_OOBS_Bits.OTGB0 */
#define IFX_INT_OOBS_OTGB0_MSK (0xffffu)

/** \brief Offset for Ifx_INT_OOBS_Bits.OTGB0 */
#define IFX_INT_OOBS_OTGB0_OFF (0u)

/** \brief Length for Ifx_INT_OOBS_Bits.OTGB1 */
#define IFX_INT_OOBS_OTGB1_LEN (16u)

/** \brief Mask for Ifx_INT_OOBS_Bits.OTGB1 */
#define IFX_INT_OOBS_OTGB1_MSK (0xffffu)

/** \brief Offset for Ifx_INT_OOBS_Bits.OTGB1 */
#define IFX_INT_OOBS_OTGB1_OFF (16u)

/** \brief Length for Ifx_INT_OSSIC_Bits.TGS */
#define IFX_INT_OSSIC_TGS_LEN (2u)

/** \brief Mask for Ifx_INT_OSSIC_Bits.TGS */
#define IFX_INT_OSSIC_TGS_MSK (0x3u)

/** \brief Offset for Ifx_INT_OSSIC_Bits.TGS */
#define IFX_INT_OSSIC_TGS_OFF (0u)

/** \brief Length for Ifx_INT_OSSIC_Bits.TGB */
#define IFX_INT_OSSIC_TGB_LEN (1u)

/** \brief Mask for Ifx_INT_OSSIC_Bits.TGB */
#define IFX_INT_OSSIC_TGB_MSK (0x1u)

/** \brief Offset for Ifx_INT_OSSIC_Bits.TGB */
#define IFX_INT_OSSIC_TGB_OFF (2u)

/** \brief Length for Ifx_INT_OIXTS_Bits.TGS */
#define IFX_INT_OIXTS_TGS_LEN (2u)

/** \brief Mask for Ifx_INT_OIXTS_Bits.TGS */
#define IFX_INT_OIXTS_TGS_MSK (0x3u)

/** \brief Offset for Ifx_INT_OIXTS_Bits.TGS */
#define IFX_INT_OIXTS_TGS_OFF (0u)

/** \brief Length for Ifx_INT_OIXTS_Bits.OBS */
#define IFX_INT_OIXTS_OBS_LEN (2u)

/** \brief Mask for Ifx_INT_OIXTS_Bits.OBS */
#define IFX_INT_OIXTS_OBS_MSK (0x3u)

/** \brief Offset for Ifx_INT_OIXTS_Bits.OBS */
#define IFX_INT_OIXTS_OBS_OFF (8u)

/** \brief Length for Ifx_INT_OIXMS_Bits.MIRQ */
#define IFX_INT_OIXMS_MIRQ_LEN (10u)

/** \brief Mask for Ifx_INT_OIXMS_Bits.MIRQ */
#define IFX_INT_OIXMS_MIRQ_MSK (0x3ffu)

/** \brief Offset for Ifx_INT_OIXMS_Bits.MIRQ */
#define IFX_INT_OIXMS_MIRQ_OFF (0u)

/** \brief Length for Ifx_INT_OIXS0_Bits.IRQ0 */
#define IFX_INT_OIXS0_IRQ0_LEN (10u)

/** \brief Mask for Ifx_INT_OIXS0_Bits.IRQ0 */
#define IFX_INT_OIXS0_IRQ0_MSK (0x3ffu)

/** \brief Offset for Ifx_INT_OIXS0_Bits.IRQ0 */
#define IFX_INT_OIXS0_IRQ0_OFF (0u)

/** \brief Length for Ifx_INT_OIXS0_Bits.IRQ1 */
#define IFX_INT_OIXS0_IRQ1_LEN (10u)

/** \brief Mask for Ifx_INT_OIXS0_Bits.IRQ1 */
#define IFX_INT_OIXS0_IRQ1_MSK (0x3ffu)

/** \brief Offset for Ifx_INT_OIXS0_Bits.IRQ1 */
#define IFX_INT_OIXS0_IRQ1_OFF (16u)

/** \brief Length for Ifx_INT_OIXS1_Bits.IRQ2 */
#define IFX_INT_OIXS1_IRQ2_LEN (10u)

/** \brief Mask for Ifx_INT_OIXS1_Bits.IRQ2 */
#define IFX_INT_OIXS1_IRQ2_MSK (0x3ffu)

/** \brief Offset for Ifx_INT_OIXS1_Bits.IRQ2 */
#define IFX_INT_OIXS1_IRQ2_OFF (0u)

/** \brief Length for Ifx_INT_OIXS1_Bits.IRQ3 */
#define IFX_INT_OIXS1_IRQ3_LEN (10u)

/** \brief Mask for Ifx_INT_OIXS1_Bits.IRQ3 */
#define IFX_INT_OIXS1_IRQ3_MSK (0x3ffu)

/** \brief Offset for Ifx_INT_OIXS1_Bits.IRQ3 */
#define IFX_INT_OIXS1_IRQ3_OFF (16u)

/** \brief Length for Ifx_INT_OIT_Bits.TOS0 */
#define IFX_INT_OIT_TOS0_LEN (3u)

/** \brief Mask for Ifx_INT_OIT_Bits.TOS0 */
#define IFX_INT_OIT_TOS0_MSK (0x7u)

/** \brief Offset for Ifx_INT_OIT_Bits.TOS0 */
#define IFX_INT_OIT_TOS0_OFF (0u)

/** \brief Length for Ifx_INT_OIT_Bits.OE0 */
#define IFX_INT_OIT_OE0_LEN (1u)

/** \brief Mask for Ifx_INT_OIT_Bits.OE0 */
#define IFX_INT_OIT_OE0_MSK (0x1u)

/** \brief Offset for Ifx_INT_OIT_Bits.OE0 */
#define IFX_INT_OIT_OE0_OFF (7u)

/** \brief Length for Ifx_INT_OIT_Bits.TOS1 */
#define IFX_INT_OIT_TOS1_LEN (3u)

/** \brief Mask for Ifx_INT_OIT_Bits.TOS1 */
#define IFX_INT_OIT_TOS1_MSK (0x7u)

/** \brief Offset for Ifx_INT_OIT_Bits.TOS1 */
#define IFX_INT_OIT_TOS1_OFF (8u)

/** \brief Length for Ifx_INT_OIT_Bits.OE1 */
#define IFX_INT_OIT_OE1_LEN (1u)

/** \brief Mask for Ifx_INT_OIT_Bits.OE1 */
#define IFX_INT_OIT_OE1_MSK (0x1u)

/** \brief Offset for Ifx_INT_OIT_Bits.OE1 */
#define IFX_INT_OIT_OE1_OFF (15u)

/** \brief Length for Ifx_INT_OMISP_Bits.OTGB0 */
#define IFX_INT_OMISP_OTGB0_LEN (16u)

/** \brief Mask for Ifx_INT_OMISP_Bits.OTGB0 */
#define IFX_INT_OMISP_OTGB0_MSK (0xffffu)

/** \brief Offset for Ifx_INT_OMISP_Bits.OTGB0 */
#define IFX_INT_OMISP_OTGB0_OFF (0u)

/** \brief Length for Ifx_INT_OMISP_Bits.OTGB1 */
#define IFX_INT_OMISP_OTGB1_LEN (16u)

/** \brief Mask for Ifx_INT_OMISP_Bits.OTGB1 */
#define IFX_INT_OMISP_OTGB1_MSK (0xffffu)

/** \brief Offset for Ifx_INT_OMISP_Bits.OTGB1 */
#define IFX_INT_OMISP_OTGB1_OFF (16u)

/** \brief Length for Ifx_INT_OMISN_Bits.OTGB0 */
#define IFX_INT_OMISN_OTGB0_LEN (16u)

/** \brief Mask for Ifx_INT_OMISN_Bits.OTGB0 */
#define IFX_INT_OMISN_OTGB0_MSK (0xffffu)

/** \brief Offset for Ifx_INT_OMISN_Bits.OTGB0 */
#define IFX_INT_OMISN_OTGB0_OFF (0u)

/** \brief Length for Ifx_INT_OMISN_Bits.OTGB1 */
#define IFX_INT_OMISN_OTGB1_LEN (16u)

/** \brief Mask for Ifx_INT_OMISN_Bits.OTGB1 */
#define IFX_INT_OMISN_OTGB1_MSK (0xffffu)

/** \brief Offset for Ifx_INT_OMISN_Bits.OTGB1 */
#define IFX_INT_OMISN_OTGB1_OFF (16u)

/** \brief Length for Ifx_INT_ACCEN_CONFIG0_Bits.EN0 */
#define IFX_INT_ACCEN_CONFIG0_EN0_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_CONFIG0_Bits.EN0 */
#define IFX_INT_ACCEN_CONFIG0_EN0_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_CONFIG0_Bits.EN0 */
#define IFX_INT_ACCEN_CONFIG0_EN0_OFF (0u)

/** \brief Length for Ifx_INT_ACCEN_CONFIG0_Bits.EN1 */
#define IFX_INT_ACCEN_CONFIG0_EN1_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_CONFIG0_Bits.EN1 */
#define IFX_INT_ACCEN_CONFIG0_EN1_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_CONFIG0_Bits.EN1 */
#define IFX_INT_ACCEN_CONFIG0_EN1_OFF (1u)

/** \brief Length for Ifx_INT_ACCEN_CONFIG0_Bits.EN2 */
#define IFX_INT_ACCEN_CONFIG0_EN2_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_CONFIG0_Bits.EN2 */
#define IFX_INT_ACCEN_CONFIG0_EN2_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_CONFIG0_Bits.EN2 */
#define IFX_INT_ACCEN_CONFIG0_EN2_OFF (2u)

/** \brief Length for Ifx_INT_ACCEN_CONFIG0_Bits.EN3 */
#define IFX_INT_ACCEN_CONFIG0_EN3_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_CONFIG0_Bits.EN3 */
#define IFX_INT_ACCEN_CONFIG0_EN3_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_CONFIG0_Bits.EN3 */
#define IFX_INT_ACCEN_CONFIG0_EN3_OFF (3u)

/** \brief Length for Ifx_INT_ACCEN_CONFIG0_Bits.EN4 */
#define IFX_INT_ACCEN_CONFIG0_EN4_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_CONFIG0_Bits.EN4 */
#define IFX_INT_ACCEN_CONFIG0_EN4_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_CONFIG0_Bits.EN4 */
#define IFX_INT_ACCEN_CONFIG0_EN4_OFF (4u)

/** \brief Length for Ifx_INT_ACCEN_CONFIG0_Bits.EN5 */
#define IFX_INT_ACCEN_CONFIG0_EN5_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_CONFIG0_Bits.EN5 */
#define IFX_INT_ACCEN_CONFIG0_EN5_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_CONFIG0_Bits.EN5 */
#define IFX_INT_ACCEN_CONFIG0_EN5_OFF (5u)

/** \brief Length for Ifx_INT_ACCEN_CONFIG0_Bits.EN6 */
#define IFX_INT_ACCEN_CONFIG0_EN6_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_CONFIG0_Bits.EN6 */
#define IFX_INT_ACCEN_CONFIG0_EN6_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_CONFIG0_Bits.EN6 */
#define IFX_INT_ACCEN_CONFIG0_EN6_OFF (6u)

/** \brief Length for Ifx_INT_ACCEN_CONFIG0_Bits.EN7 */
#define IFX_INT_ACCEN_CONFIG0_EN7_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_CONFIG0_Bits.EN7 */
#define IFX_INT_ACCEN_CONFIG0_EN7_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_CONFIG0_Bits.EN7 */
#define IFX_INT_ACCEN_CONFIG0_EN7_OFF (7u)

/** \brief Length for Ifx_INT_ACCEN_CONFIG0_Bits.EN8 */
#define IFX_INT_ACCEN_CONFIG0_EN8_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_CONFIG0_Bits.EN8 */
#define IFX_INT_ACCEN_CONFIG0_EN8_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_CONFIG0_Bits.EN8 */
#define IFX_INT_ACCEN_CONFIG0_EN8_OFF (8u)

/** \brief Length for Ifx_INT_ACCEN_CONFIG0_Bits.EN9 */
#define IFX_INT_ACCEN_CONFIG0_EN9_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_CONFIG0_Bits.EN9 */
#define IFX_INT_ACCEN_CONFIG0_EN9_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_CONFIG0_Bits.EN9 */
#define IFX_INT_ACCEN_CONFIG0_EN9_OFF (9u)

/** \brief Length for Ifx_INT_ACCEN_CONFIG0_Bits.EN10 */
#define IFX_INT_ACCEN_CONFIG0_EN10_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_CONFIG0_Bits.EN10 */
#define IFX_INT_ACCEN_CONFIG0_EN10_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_CONFIG0_Bits.EN10 */
#define IFX_INT_ACCEN_CONFIG0_EN10_OFF (10u)

/** \brief Length for Ifx_INT_ACCEN_CONFIG0_Bits.EN11 */
#define IFX_INT_ACCEN_CONFIG0_EN11_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_CONFIG0_Bits.EN11 */
#define IFX_INT_ACCEN_CONFIG0_EN11_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_CONFIG0_Bits.EN11 */
#define IFX_INT_ACCEN_CONFIG0_EN11_OFF (11u)

/** \brief Length for Ifx_INT_ACCEN_CONFIG0_Bits.EN12 */
#define IFX_INT_ACCEN_CONFIG0_EN12_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_CONFIG0_Bits.EN12 */
#define IFX_INT_ACCEN_CONFIG0_EN12_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_CONFIG0_Bits.EN12 */
#define IFX_INT_ACCEN_CONFIG0_EN12_OFF (12u)

/** \brief Length for Ifx_INT_ACCEN_CONFIG0_Bits.EN13 */
#define IFX_INT_ACCEN_CONFIG0_EN13_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_CONFIG0_Bits.EN13 */
#define IFX_INT_ACCEN_CONFIG0_EN13_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_CONFIG0_Bits.EN13 */
#define IFX_INT_ACCEN_CONFIG0_EN13_OFF (13u)

/** \brief Length for Ifx_INT_ACCEN_CONFIG0_Bits.EN14 */
#define IFX_INT_ACCEN_CONFIG0_EN14_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_CONFIG0_Bits.EN14 */
#define IFX_INT_ACCEN_CONFIG0_EN14_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_CONFIG0_Bits.EN14 */
#define IFX_INT_ACCEN_CONFIG0_EN14_OFF (14u)

/** \brief Length for Ifx_INT_ACCEN_CONFIG0_Bits.EN15 */
#define IFX_INT_ACCEN_CONFIG0_EN15_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_CONFIG0_Bits.EN15 */
#define IFX_INT_ACCEN_CONFIG0_EN15_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_CONFIG0_Bits.EN15 */
#define IFX_INT_ACCEN_CONFIG0_EN15_OFF (15u)

/** \brief Length for Ifx_INT_ACCEN_CONFIG0_Bits.EN16 */
#define IFX_INT_ACCEN_CONFIG0_EN16_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_CONFIG0_Bits.EN16 */
#define IFX_INT_ACCEN_CONFIG0_EN16_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_CONFIG0_Bits.EN16 */
#define IFX_INT_ACCEN_CONFIG0_EN16_OFF (16u)

/** \brief Length for Ifx_INT_ACCEN_CONFIG0_Bits.EN17 */
#define IFX_INT_ACCEN_CONFIG0_EN17_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_CONFIG0_Bits.EN17 */
#define IFX_INT_ACCEN_CONFIG0_EN17_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_CONFIG0_Bits.EN17 */
#define IFX_INT_ACCEN_CONFIG0_EN17_OFF (17u)

/** \brief Length for Ifx_INT_ACCEN_CONFIG0_Bits.EN18 */
#define IFX_INT_ACCEN_CONFIG0_EN18_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_CONFIG0_Bits.EN18 */
#define IFX_INT_ACCEN_CONFIG0_EN18_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_CONFIG0_Bits.EN18 */
#define IFX_INT_ACCEN_CONFIG0_EN18_OFF (18u)

/** \brief Length for Ifx_INT_ACCEN_CONFIG0_Bits.EN19 */
#define IFX_INT_ACCEN_CONFIG0_EN19_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_CONFIG0_Bits.EN19 */
#define IFX_INT_ACCEN_CONFIG0_EN19_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_CONFIG0_Bits.EN19 */
#define IFX_INT_ACCEN_CONFIG0_EN19_OFF (19u)

/** \brief Length for Ifx_INT_ACCEN_CONFIG0_Bits.EN20 */
#define IFX_INT_ACCEN_CONFIG0_EN20_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_CONFIG0_Bits.EN20 */
#define IFX_INT_ACCEN_CONFIG0_EN20_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_CONFIG0_Bits.EN20 */
#define IFX_INT_ACCEN_CONFIG0_EN20_OFF (20u)

/** \brief Length for Ifx_INT_ACCEN_CONFIG0_Bits.EN21 */
#define IFX_INT_ACCEN_CONFIG0_EN21_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_CONFIG0_Bits.EN21 */
#define IFX_INT_ACCEN_CONFIG0_EN21_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_CONFIG0_Bits.EN21 */
#define IFX_INT_ACCEN_CONFIG0_EN21_OFF (21u)

/** \brief Length for Ifx_INT_ACCEN_CONFIG0_Bits.EN22 */
#define IFX_INT_ACCEN_CONFIG0_EN22_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_CONFIG0_Bits.EN22 */
#define IFX_INT_ACCEN_CONFIG0_EN22_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_CONFIG0_Bits.EN22 */
#define IFX_INT_ACCEN_CONFIG0_EN22_OFF (22u)

/** \brief Length for Ifx_INT_ACCEN_CONFIG0_Bits.EN23 */
#define IFX_INT_ACCEN_CONFIG0_EN23_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_CONFIG0_Bits.EN23 */
#define IFX_INT_ACCEN_CONFIG0_EN23_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_CONFIG0_Bits.EN23 */
#define IFX_INT_ACCEN_CONFIG0_EN23_OFF (23u)

/** \brief Length for Ifx_INT_ACCEN_CONFIG0_Bits.EN24 */
#define IFX_INT_ACCEN_CONFIG0_EN24_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_CONFIG0_Bits.EN24 */
#define IFX_INT_ACCEN_CONFIG0_EN24_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_CONFIG0_Bits.EN24 */
#define IFX_INT_ACCEN_CONFIG0_EN24_OFF (24u)

/** \brief Length for Ifx_INT_ACCEN_CONFIG0_Bits.EN25 */
#define IFX_INT_ACCEN_CONFIG0_EN25_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_CONFIG0_Bits.EN25 */
#define IFX_INT_ACCEN_CONFIG0_EN25_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_CONFIG0_Bits.EN25 */
#define IFX_INT_ACCEN_CONFIG0_EN25_OFF (25u)

/** \brief Length for Ifx_INT_ACCEN_CONFIG0_Bits.EN26 */
#define IFX_INT_ACCEN_CONFIG0_EN26_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_CONFIG0_Bits.EN26 */
#define IFX_INT_ACCEN_CONFIG0_EN26_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_CONFIG0_Bits.EN26 */
#define IFX_INT_ACCEN_CONFIG0_EN26_OFF (26u)

/** \brief Length for Ifx_INT_ACCEN_CONFIG0_Bits.EN27 */
#define IFX_INT_ACCEN_CONFIG0_EN27_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_CONFIG0_Bits.EN27 */
#define IFX_INT_ACCEN_CONFIG0_EN27_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_CONFIG0_Bits.EN27 */
#define IFX_INT_ACCEN_CONFIG0_EN27_OFF (27u)

/** \brief Length for Ifx_INT_ACCEN_CONFIG0_Bits.EN28 */
#define IFX_INT_ACCEN_CONFIG0_EN28_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_CONFIG0_Bits.EN28 */
#define IFX_INT_ACCEN_CONFIG0_EN28_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_CONFIG0_Bits.EN28 */
#define IFX_INT_ACCEN_CONFIG0_EN28_OFF (28u)

/** \brief Length for Ifx_INT_ACCEN_CONFIG0_Bits.EN29 */
#define IFX_INT_ACCEN_CONFIG0_EN29_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_CONFIG0_Bits.EN29 */
#define IFX_INT_ACCEN_CONFIG0_EN29_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_CONFIG0_Bits.EN29 */
#define IFX_INT_ACCEN_CONFIG0_EN29_OFF (29u)

/** \brief Length for Ifx_INT_ACCEN_CONFIG0_Bits.EN30 */
#define IFX_INT_ACCEN_CONFIG0_EN30_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_CONFIG0_Bits.EN30 */
#define IFX_INT_ACCEN_CONFIG0_EN30_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_CONFIG0_Bits.EN30 */
#define IFX_INT_ACCEN_CONFIG0_EN30_OFF (30u)

/** \brief Length for Ifx_INT_ACCEN_CONFIG0_Bits.EN31 */
#define IFX_INT_ACCEN_CONFIG0_EN31_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_CONFIG0_Bits.EN31 */
#define IFX_INT_ACCEN_CONFIG0_EN31_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_CONFIG0_Bits.EN31 */
#define IFX_INT_ACCEN_CONFIG0_EN31_OFF (31u)

/** \brief Length for Ifx_INT_ACCEN_SRB0_Bits.EN0 */
#define IFX_INT_ACCEN_SRB0_EN0_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRB0_Bits.EN0 */
#define IFX_INT_ACCEN_SRB0_EN0_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRB0_Bits.EN0 */
#define IFX_INT_ACCEN_SRB0_EN0_OFF (0u)

/** \brief Length for Ifx_INT_ACCEN_SRB0_Bits.EN1 */
#define IFX_INT_ACCEN_SRB0_EN1_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRB0_Bits.EN1 */
#define IFX_INT_ACCEN_SRB0_EN1_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRB0_Bits.EN1 */
#define IFX_INT_ACCEN_SRB0_EN1_OFF (1u)

/** \brief Length for Ifx_INT_ACCEN_SRB0_Bits.EN2 */
#define IFX_INT_ACCEN_SRB0_EN2_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRB0_Bits.EN2 */
#define IFX_INT_ACCEN_SRB0_EN2_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRB0_Bits.EN2 */
#define IFX_INT_ACCEN_SRB0_EN2_OFF (2u)

/** \brief Length for Ifx_INT_ACCEN_SRB0_Bits.EN3 */
#define IFX_INT_ACCEN_SRB0_EN3_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRB0_Bits.EN3 */
#define IFX_INT_ACCEN_SRB0_EN3_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRB0_Bits.EN3 */
#define IFX_INT_ACCEN_SRB0_EN3_OFF (3u)

/** \brief Length for Ifx_INT_ACCEN_SRB0_Bits.EN4 */
#define IFX_INT_ACCEN_SRB0_EN4_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRB0_Bits.EN4 */
#define IFX_INT_ACCEN_SRB0_EN4_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRB0_Bits.EN4 */
#define IFX_INT_ACCEN_SRB0_EN4_OFF (4u)

/** \brief Length for Ifx_INT_ACCEN_SRB0_Bits.EN5 */
#define IFX_INT_ACCEN_SRB0_EN5_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRB0_Bits.EN5 */
#define IFX_INT_ACCEN_SRB0_EN5_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRB0_Bits.EN5 */
#define IFX_INT_ACCEN_SRB0_EN5_OFF (5u)

/** \brief Length for Ifx_INT_ACCEN_SRB0_Bits.EN6 */
#define IFX_INT_ACCEN_SRB0_EN6_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRB0_Bits.EN6 */
#define IFX_INT_ACCEN_SRB0_EN6_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRB0_Bits.EN6 */
#define IFX_INT_ACCEN_SRB0_EN6_OFF (6u)

/** \brief Length for Ifx_INT_ACCEN_SRB0_Bits.EN7 */
#define IFX_INT_ACCEN_SRB0_EN7_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRB0_Bits.EN7 */
#define IFX_INT_ACCEN_SRB0_EN7_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRB0_Bits.EN7 */
#define IFX_INT_ACCEN_SRB0_EN7_OFF (7u)

/** \brief Length for Ifx_INT_ACCEN_SRB0_Bits.EN8 */
#define IFX_INT_ACCEN_SRB0_EN8_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRB0_Bits.EN8 */
#define IFX_INT_ACCEN_SRB0_EN8_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRB0_Bits.EN8 */
#define IFX_INT_ACCEN_SRB0_EN8_OFF (8u)

/** \brief Length for Ifx_INT_ACCEN_SRB0_Bits.EN9 */
#define IFX_INT_ACCEN_SRB0_EN9_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRB0_Bits.EN9 */
#define IFX_INT_ACCEN_SRB0_EN9_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRB0_Bits.EN9 */
#define IFX_INT_ACCEN_SRB0_EN9_OFF (9u)

/** \brief Length for Ifx_INT_ACCEN_SRB0_Bits.EN10 */
#define IFX_INT_ACCEN_SRB0_EN10_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRB0_Bits.EN10 */
#define IFX_INT_ACCEN_SRB0_EN10_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRB0_Bits.EN10 */
#define IFX_INT_ACCEN_SRB0_EN10_OFF (10u)

/** \brief Length for Ifx_INT_ACCEN_SRB0_Bits.EN11 */
#define IFX_INT_ACCEN_SRB0_EN11_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRB0_Bits.EN11 */
#define IFX_INT_ACCEN_SRB0_EN11_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRB0_Bits.EN11 */
#define IFX_INT_ACCEN_SRB0_EN11_OFF (11u)

/** \brief Length for Ifx_INT_ACCEN_SRB0_Bits.EN12 */
#define IFX_INT_ACCEN_SRB0_EN12_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRB0_Bits.EN12 */
#define IFX_INT_ACCEN_SRB0_EN12_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRB0_Bits.EN12 */
#define IFX_INT_ACCEN_SRB0_EN12_OFF (12u)

/** \brief Length for Ifx_INT_ACCEN_SRB0_Bits.EN13 */
#define IFX_INT_ACCEN_SRB0_EN13_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRB0_Bits.EN13 */
#define IFX_INT_ACCEN_SRB0_EN13_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRB0_Bits.EN13 */
#define IFX_INT_ACCEN_SRB0_EN13_OFF (13u)

/** \brief Length for Ifx_INT_ACCEN_SRB0_Bits.EN14 */
#define IFX_INT_ACCEN_SRB0_EN14_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRB0_Bits.EN14 */
#define IFX_INT_ACCEN_SRB0_EN14_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRB0_Bits.EN14 */
#define IFX_INT_ACCEN_SRB0_EN14_OFF (14u)

/** \brief Length for Ifx_INT_ACCEN_SRB0_Bits.EN15 */
#define IFX_INT_ACCEN_SRB0_EN15_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRB0_Bits.EN15 */
#define IFX_INT_ACCEN_SRB0_EN15_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRB0_Bits.EN15 */
#define IFX_INT_ACCEN_SRB0_EN15_OFF (15u)

/** \brief Length for Ifx_INT_ACCEN_SRB0_Bits.EN16 */
#define IFX_INT_ACCEN_SRB0_EN16_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRB0_Bits.EN16 */
#define IFX_INT_ACCEN_SRB0_EN16_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRB0_Bits.EN16 */
#define IFX_INT_ACCEN_SRB0_EN16_OFF (16u)

/** \brief Length for Ifx_INT_ACCEN_SRB0_Bits.EN17 */
#define IFX_INT_ACCEN_SRB0_EN17_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRB0_Bits.EN17 */
#define IFX_INT_ACCEN_SRB0_EN17_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRB0_Bits.EN17 */
#define IFX_INT_ACCEN_SRB0_EN17_OFF (17u)

/** \brief Length for Ifx_INT_ACCEN_SRB0_Bits.EN18 */
#define IFX_INT_ACCEN_SRB0_EN18_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRB0_Bits.EN18 */
#define IFX_INT_ACCEN_SRB0_EN18_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRB0_Bits.EN18 */
#define IFX_INT_ACCEN_SRB0_EN18_OFF (18u)

/** \brief Length for Ifx_INT_ACCEN_SRB0_Bits.EN19 */
#define IFX_INT_ACCEN_SRB0_EN19_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRB0_Bits.EN19 */
#define IFX_INT_ACCEN_SRB0_EN19_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRB0_Bits.EN19 */
#define IFX_INT_ACCEN_SRB0_EN19_OFF (19u)

/** \brief Length for Ifx_INT_ACCEN_SRB0_Bits.EN20 */
#define IFX_INT_ACCEN_SRB0_EN20_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRB0_Bits.EN20 */
#define IFX_INT_ACCEN_SRB0_EN20_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRB0_Bits.EN20 */
#define IFX_INT_ACCEN_SRB0_EN20_OFF (20u)

/** \brief Length for Ifx_INT_ACCEN_SRB0_Bits.EN21 */
#define IFX_INT_ACCEN_SRB0_EN21_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRB0_Bits.EN21 */
#define IFX_INT_ACCEN_SRB0_EN21_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRB0_Bits.EN21 */
#define IFX_INT_ACCEN_SRB0_EN21_OFF (21u)

/** \brief Length for Ifx_INT_ACCEN_SRB0_Bits.EN22 */
#define IFX_INT_ACCEN_SRB0_EN22_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRB0_Bits.EN22 */
#define IFX_INT_ACCEN_SRB0_EN22_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRB0_Bits.EN22 */
#define IFX_INT_ACCEN_SRB0_EN22_OFF (22u)

/** \brief Length for Ifx_INT_ACCEN_SRB0_Bits.EN23 */
#define IFX_INT_ACCEN_SRB0_EN23_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRB0_Bits.EN23 */
#define IFX_INT_ACCEN_SRB0_EN23_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRB0_Bits.EN23 */
#define IFX_INT_ACCEN_SRB0_EN23_OFF (23u)

/** \brief Length for Ifx_INT_ACCEN_SRB0_Bits.EN24 */
#define IFX_INT_ACCEN_SRB0_EN24_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRB0_Bits.EN24 */
#define IFX_INT_ACCEN_SRB0_EN24_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRB0_Bits.EN24 */
#define IFX_INT_ACCEN_SRB0_EN24_OFF (24u)

/** \brief Length for Ifx_INT_ACCEN_SRB0_Bits.EN25 */
#define IFX_INT_ACCEN_SRB0_EN25_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRB0_Bits.EN25 */
#define IFX_INT_ACCEN_SRB0_EN25_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRB0_Bits.EN25 */
#define IFX_INT_ACCEN_SRB0_EN25_OFF (25u)

/** \brief Length for Ifx_INT_ACCEN_SRB0_Bits.EN26 */
#define IFX_INT_ACCEN_SRB0_EN26_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRB0_Bits.EN26 */
#define IFX_INT_ACCEN_SRB0_EN26_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRB0_Bits.EN26 */
#define IFX_INT_ACCEN_SRB0_EN26_OFF (26u)

/** \brief Length for Ifx_INT_ACCEN_SRB0_Bits.EN27 */
#define IFX_INT_ACCEN_SRB0_EN27_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRB0_Bits.EN27 */
#define IFX_INT_ACCEN_SRB0_EN27_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRB0_Bits.EN27 */
#define IFX_INT_ACCEN_SRB0_EN27_OFF (27u)

/** \brief Length for Ifx_INT_ACCEN_SRB0_Bits.EN28 */
#define IFX_INT_ACCEN_SRB0_EN28_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRB0_Bits.EN28 */
#define IFX_INT_ACCEN_SRB0_EN28_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRB0_Bits.EN28 */
#define IFX_INT_ACCEN_SRB0_EN28_OFF (28u)

/** \brief Length for Ifx_INT_ACCEN_SRB0_Bits.EN29 */
#define IFX_INT_ACCEN_SRB0_EN29_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRB0_Bits.EN29 */
#define IFX_INT_ACCEN_SRB0_EN29_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRB0_Bits.EN29 */
#define IFX_INT_ACCEN_SRB0_EN29_OFF (29u)

/** \brief Length for Ifx_INT_ACCEN_SRB0_Bits.EN30 */
#define IFX_INT_ACCEN_SRB0_EN30_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRB0_Bits.EN30 */
#define IFX_INT_ACCEN_SRB0_EN30_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRB0_Bits.EN30 */
#define IFX_INT_ACCEN_SRB0_EN30_OFF (30u)

/** \brief Length for Ifx_INT_ACCEN_SRB0_Bits.EN31 */
#define IFX_INT_ACCEN_SRB0_EN31_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRB0_Bits.EN31 */
#define IFX_INT_ACCEN_SRB0_EN31_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRB0_Bits.EN31 */
#define IFX_INT_ACCEN_SRB0_EN31_OFF (31u)

/** \brief Length for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN0 */
#define IFX_INT_ACCEN_SRC_TOS0_EN0_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN0 */
#define IFX_INT_ACCEN_SRC_TOS0_EN0_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN0 */
#define IFX_INT_ACCEN_SRC_TOS0_EN0_OFF (0u)

/** \brief Length for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN1 */
#define IFX_INT_ACCEN_SRC_TOS0_EN1_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN1 */
#define IFX_INT_ACCEN_SRC_TOS0_EN1_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN1 */
#define IFX_INT_ACCEN_SRC_TOS0_EN1_OFF (1u)

/** \brief Length for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN2 */
#define IFX_INT_ACCEN_SRC_TOS0_EN2_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN2 */
#define IFX_INT_ACCEN_SRC_TOS0_EN2_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN2 */
#define IFX_INT_ACCEN_SRC_TOS0_EN2_OFF (2u)

/** \brief Length for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN3 */
#define IFX_INT_ACCEN_SRC_TOS0_EN3_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN3 */
#define IFX_INT_ACCEN_SRC_TOS0_EN3_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN3 */
#define IFX_INT_ACCEN_SRC_TOS0_EN3_OFF (3u)

/** \brief Length for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN4 */
#define IFX_INT_ACCEN_SRC_TOS0_EN4_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN4 */
#define IFX_INT_ACCEN_SRC_TOS0_EN4_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN4 */
#define IFX_INT_ACCEN_SRC_TOS0_EN4_OFF (4u)

/** \brief Length for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN5 */
#define IFX_INT_ACCEN_SRC_TOS0_EN5_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN5 */
#define IFX_INT_ACCEN_SRC_TOS0_EN5_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN5 */
#define IFX_INT_ACCEN_SRC_TOS0_EN5_OFF (5u)

/** \brief Length for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN6 */
#define IFX_INT_ACCEN_SRC_TOS0_EN6_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN6 */
#define IFX_INT_ACCEN_SRC_TOS0_EN6_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN6 */
#define IFX_INT_ACCEN_SRC_TOS0_EN6_OFF (6u)

/** \brief Length for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN7 */
#define IFX_INT_ACCEN_SRC_TOS0_EN7_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN7 */
#define IFX_INT_ACCEN_SRC_TOS0_EN7_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN7 */
#define IFX_INT_ACCEN_SRC_TOS0_EN7_OFF (7u)

/** \brief Length for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN8 */
#define IFX_INT_ACCEN_SRC_TOS0_EN8_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN8 */
#define IFX_INT_ACCEN_SRC_TOS0_EN8_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN8 */
#define IFX_INT_ACCEN_SRC_TOS0_EN8_OFF (8u)

/** \brief Length for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN9 */
#define IFX_INT_ACCEN_SRC_TOS0_EN9_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN9 */
#define IFX_INT_ACCEN_SRC_TOS0_EN9_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN9 */
#define IFX_INT_ACCEN_SRC_TOS0_EN9_OFF (9u)

/** \brief Length for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN10 */
#define IFX_INT_ACCEN_SRC_TOS0_EN10_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN10 */
#define IFX_INT_ACCEN_SRC_TOS0_EN10_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN10 */
#define IFX_INT_ACCEN_SRC_TOS0_EN10_OFF (10u)

/** \brief Length for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN11 */
#define IFX_INT_ACCEN_SRC_TOS0_EN11_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN11 */
#define IFX_INT_ACCEN_SRC_TOS0_EN11_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN11 */
#define IFX_INT_ACCEN_SRC_TOS0_EN11_OFF (11u)

/** \brief Length for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN12 */
#define IFX_INT_ACCEN_SRC_TOS0_EN12_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN12 */
#define IFX_INT_ACCEN_SRC_TOS0_EN12_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN12 */
#define IFX_INT_ACCEN_SRC_TOS0_EN12_OFF (12u)

/** \brief Length for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN13 */
#define IFX_INT_ACCEN_SRC_TOS0_EN13_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN13 */
#define IFX_INT_ACCEN_SRC_TOS0_EN13_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN13 */
#define IFX_INT_ACCEN_SRC_TOS0_EN13_OFF (13u)

/** \brief Length for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN14 */
#define IFX_INT_ACCEN_SRC_TOS0_EN14_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN14 */
#define IFX_INT_ACCEN_SRC_TOS0_EN14_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN14 */
#define IFX_INT_ACCEN_SRC_TOS0_EN14_OFF (14u)

/** \brief Length for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN15 */
#define IFX_INT_ACCEN_SRC_TOS0_EN15_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN15 */
#define IFX_INT_ACCEN_SRC_TOS0_EN15_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN15 */
#define IFX_INT_ACCEN_SRC_TOS0_EN15_OFF (15u)

/** \brief Length for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN16 */
#define IFX_INT_ACCEN_SRC_TOS0_EN16_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN16 */
#define IFX_INT_ACCEN_SRC_TOS0_EN16_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN16 */
#define IFX_INT_ACCEN_SRC_TOS0_EN16_OFF (16u)

/** \brief Length for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN17 */
#define IFX_INT_ACCEN_SRC_TOS0_EN17_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN17 */
#define IFX_INT_ACCEN_SRC_TOS0_EN17_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN17 */
#define IFX_INT_ACCEN_SRC_TOS0_EN17_OFF (17u)

/** \brief Length for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN18 */
#define IFX_INT_ACCEN_SRC_TOS0_EN18_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN18 */
#define IFX_INT_ACCEN_SRC_TOS0_EN18_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN18 */
#define IFX_INT_ACCEN_SRC_TOS0_EN18_OFF (18u)

/** \brief Length for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN19 */
#define IFX_INT_ACCEN_SRC_TOS0_EN19_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN19 */
#define IFX_INT_ACCEN_SRC_TOS0_EN19_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN19 */
#define IFX_INT_ACCEN_SRC_TOS0_EN19_OFF (19u)

/** \brief Length for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN20 */
#define IFX_INT_ACCEN_SRC_TOS0_EN20_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN20 */
#define IFX_INT_ACCEN_SRC_TOS0_EN20_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN20 */
#define IFX_INT_ACCEN_SRC_TOS0_EN20_OFF (20u)

/** \brief Length for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN21 */
#define IFX_INT_ACCEN_SRC_TOS0_EN21_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN21 */
#define IFX_INT_ACCEN_SRC_TOS0_EN21_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN21 */
#define IFX_INT_ACCEN_SRC_TOS0_EN21_OFF (21u)

/** \brief Length for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN22 */
#define IFX_INT_ACCEN_SRC_TOS0_EN22_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN22 */
#define IFX_INT_ACCEN_SRC_TOS0_EN22_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN22 */
#define IFX_INT_ACCEN_SRC_TOS0_EN22_OFF (22u)

/** \brief Length for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN23 */
#define IFX_INT_ACCEN_SRC_TOS0_EN23_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN23 */
#define IFX_INT_ACCEN_SRC_TOS0_EN23_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN23 */
#define IFX_INT_ACCEN_SRC_TOS0_EN23_OFF (23u)

/** \brief Length for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN24 */
#define IFX_INT_ACCEN_SRC_TOS0_EN24_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN24 */
#define IFX_INT_ACCEN_SRC_TOS0_EN24_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN24 */
#define IFX_INT_ACCEN_SRC_TOS0_EN24_OFF (24u)

/** \brief Length for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN25 */
#define IFX_INT_ACCEN_SRC_TOS0_EN25_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN25 */
#define IFX_INT_ACCEN_SRC_TOS0_EN25_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN25 */
#define IFX_INT_ACCEN_SRC_TOS0_EN25_OFF (25u)

/** \brief Length for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN26 */
#define IFX_INT_ACCEN_SRC_TOS0_EN26_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN26 */
#define IFX_INT_ACCEN_SRC_TOS0_EN26_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN26 */
#define IFX_INT_ACCEN_SRC_TOS0_EN26_OFF (26u)

/** \brief Length for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN27 */
#define IFX_INT_ACCEN_SRC_TOS0_EN27_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN27 */
#define IFX_INT_ACCEN_SRC_TOS0_EN27_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN27 */
#define IFX_INT_ACCEN_SRC_TOS0_EN27_OFF (27u)

/** \brief Length for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN28 */
#define IFX_INT_ACCEN_SRC_TOS0_EN28_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN28 */
#define IFX_INT_ACCEN_SRC_TOS0_EN28_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN28 */
#define IFX_INT_ACCEN_SRC_TOS0_EN28_OFF (28u)

/** \brief Length for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN29 */
#define IFX_INT_ACCEN_SRC_TOS0_EN29_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN29 */
#define IFX_INT_ACCEN_SRC_TOS0_EN29_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN29 */
#define IFX_INT_ACCEN_SRC_TOS0_EN29_OFF (29u)

/** \brief Length for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN30 */
#define IFX_INT_ACCEN_SRC_TOS0_EN30_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN30 */
#define IFX_INT_ACCEN_SRC_TOS0_EN30_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN30 */
#define IFX_INT_ACCEN_SRC_TOS0_EN30_OFF (30u)

/** \brief Length for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN31 */
#define IFX_INT_ACCEN_SRC_TOS0_EN31_LEN (1u)

/** \brief Mask for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN31 */
#define IFX_INT_ACCEN_SRC_TOS0_EN31_MSK (0x1u)

/** \brief Offset for Ifx_INT_ACCEN_SRC_TOS0_Bits.EN31 */
#define IFX_INT_ACCEN_SRC_TOS0_EN31_OFF (31u)

/** \brief Length for Ifx_INT_CH_LWSR_Bits.PN */
#define IFX_INT_CH_LWSR_PN_LEN (8u)

/** \brief Mask for Ifx_INT_CH_LWSR_Bits.PN */
#define IFX_INT_CH_LWSR_PN_MSK (0xffu)

/** \brief Offset for Ifx_INT_CH_LWSR_Bits.PN */
#define IFX_INT_CH_LWSR_PN_OFF (0u)

/** \brief Length for Ifx_INT_CH_LWSR_Bits.ECC */
#define IFX_INT_CH_LWSR_ECC_LEN (5u)

/** \brief Mask for Ifx_INT_CH_LWSR_Bits.ECC */
#define IFX_INT_CH_LWSR_ECC_MSK (0x1fu)

/** \brief Offset for Ifx_INT_CH_LWSR_Bits.ECC */
#define IFX_INT_CH_LWSR_ECC_OFF (10u)

/** \brief Length for Ifx_INT_CH_LWSR_Bits.ID */
#define IFX_INT_CH_LWSR_ID_LEN (10u)

/** \brief Mask for Ifx_INT_CH_LWSR_Bits.ID */
#define IFX_INT_CH_LWSR_ID_MSK (0x3ffu)

/** \brief Offset for Ifx_INT_CH_LWSR_Bits.ID */
#define IFX_INT_CH_LWSR_ID_OFF (16u)

/** \brief Length for Ifx_INT_CH_LWSR_Bits.STAT */
#define IFX_INT_CH_LWSR_STAT_LEN (1u)

/** \brief Mask for Ifx_INT_CH_LWSR_Bits.STAT */
#define IFX_INT_CH_LWSR_STAT_MSK (0x1u)

/** \brief Offset for Ifx_INT_CH_LWSR_Bits.STAT */
#define IFX_INT_CH_LWSR_STAT_OFF (31u)

/** \brief Length for Ifx_INT_CH_LASR_Bits.PN */
#define IFX_INT_CH_LASR_PN_LEN (8u)

/** \brief Mask for Ifx_INT_CH_LASR_Bits.PN */
#define IFX_INT_CH_LASR_PN_MSK (0xffu)

/** \brief Offset for Ifx_INT_CH_LASR_Bits.PN */
#define IFX_INT_CH_LASR_PN_OFF (0u)

/** \brief Length for Ifx_INT_CH_LASR_Bits.ECC */
#define IFX_INT_CH_LASR_ECC_LEN (5u)

/** \brief Mask for Ifx_INT_CH_LASR_Bits.ECC */
#define IFX_INT_CH_LASR_ECC_MSK (0x1fu)

/** \brief Offset for Ifx_INT_CH_LASR_Bits.ECC */
#define IFX_INT_CH_LASR_ECC_OFF (10u)

/** \brief Length for Ifx_INT_CH_LASR_Bits.ID */
#define IFX_INT_CH_LASR_ID_LEN (10u)

/** \brief Mask for Ifx_INT_CH_LASR_Bits.ID */
#define IFX_INT_CH_LASR_ID_MSK (0x3ffu)

/** \brief Offset for Ifx_INT_CH_LASR_Bits.ID */
#define IFX_INT_CH_LASR_ID_OFF (16u)

/** \brief Length for Ifx_INT_CH_ECR_Bits.PN */
#define IFX_INT_CH_ECR_PN_LEN (8u)

/** \brief Mask for Ifx_INT_CH_ECR_Bits.PN */
#define IFX_INT_CH_ECR_PN_MSK (0xffu)

/** \brief Offset for Ifx_INT_CH_ECR_Bits.PN */
#define IFX_INT_CH_ECR_PN_OFF (0u)

/** \brief Length for Ifx_INT_CH_ECR_Bits.ECC */
#define IFX_INT_CH_ECR_ECC_LEN (5u)

/** \brief Mask for Ifx_INT_CH_ECR_Bits.ECC */
#define IFX_INT_CH_ECR_ECC_MSK (0x1fu)

/** \brief Offset for Ifx_INT_CH_ECR_Bits.ECC */
#define IFX_INT_CH_ECR_ECC_OFF (10u)

/** \brief Length for Ifx_INT_CH_ECR_Bits.ID */
#define IFX_INT_CH_ECR_ID_LEN (10u)

/** \brief Mask for Ifx_INT_CH_ECR_Bits.ID */
#define IFX_INT_CH_ECR_ID_MSK (0x3ffu)

/** \brief Offset for Ifx_INT_CH_ECR_Bits.ID */
#define IFX_INT_CH_ECR_ID_OFF (16u)

/** \brief Length for Ifx_INT_CH_ECR_Bits.EOVCLR */
#define IFX_INT_CH_ECR_EOVCLR_LEN (1u)

/** \brief Mask for Ifx_INT_CH_ECR_Bits.EOVCLR */
#define IFX_INT_CH_ECR_EOVCLR_MSK (0x1u)

/** \brief Offset for Ifx_INT_CH_ECR_Bits.EOVCLR */
#define IFX_INT_CH_ECR_EOVCLR_OFF (28u)

/** \brief Length for Ifx_INT_CH_ECR_Bits.STATCLR */
#define IFX_INT_CH_ECR_STATCLR_LEN (1u)

/** \brief Mask for Ifx_INT_CH_ECR_Bits.STATCLR */
#define IFX_INT_CH_ECR_STATCLR_MSK (0x1u)

/** \brief Offset for Ifx_INT_CH_ECR_Bits.STATCLR */
#define IFX_INT_CH_ECR_STATCLR_OFF (29u)

/** \brief Length for Ifx_INT_CH_ECR_Bits.EOV */
#define IFX_INT_CH_ECR_EOV_LEN (1u)

/** \brief Mask for Ifx_INT_CH_ECR_Bits.EOV */
#define IFX_INT_CH_ECR_EOV_MSK (0x1u)

/** \brief Offset for Ifx_INT_CH_ECR_Bits.EOV */
#define IFX_INT_CH_ECR_EOV_OFF (30u)

/** \brief Length for Ifx_INT_CH_ECR_Bits.STAT */
#define IFX_INT_CH_ECR_STAT_LEN (1u)

/** \brief Mask for Ifx_INT_CH_ECR_Bits.STAT */
#define IFX_INT_CH_ECR_STAT_MSK (0x1u)

/** \brief Offset for Ifx_INT_CH_ECR_Bits.STAT */
#define IFX_INT_CH_ECR_STAT_OFF (31u)

/** \}  */

/******************************************************************************/

/******************************************************************************/

#endif /* IFXINT_BF_H */
